1. Field of the Invention
The present invention relates to a liquid crystal display or other matrix-type display apparatus suited to using a multiple line selection drive method, and relates specifically to an improvement of primarily the matrix-type display element module, controller, and signal electrode driver circuit.
2. Related Art
In a simple matrix-type liquid crystal display commonly used for flat panel display devices, the display data from a microprocessor unit (MPU) is typically transferred to the LCD module (the liquid crystal display panel (LCD panel)), the scan electrode drive circuit (Y driver), and the signal electrode drive circuit (X driver) using one of two basic methods: using a matrix-type liquid crystal display element module controller (simply xe2x80x9cmodule controllerxe2x80x9d below), or using an X driver embedded in RAM.
The module controller method is described first. As with a CRT display apparatus, the module controller connected to the system bus reads the display data from video RAM (VRAM), and sends the data to the LCD module at a high frequency to refresh the display.
In the latter method, a dual port frame memory (built-in RAM) is provided in the X driver. This frame memory is directly accessed by the MPU via the data bus, control bus, or address bus irrespective of the LCD timing to generate the required control signal in the X driver by changing the display data in the frame memory. One scan line equivalent of display data is simultaneously read from the built-in frame memory to refresh the display.
With the module controller method above, VRAM data access and transfer coordinated with the LCD timing must be executed each time the display screen is changed, and it is therefore necessary for the VRAM, module controller, and LCD driver to constantly operate at a high frequency. In addition, the display refresh operation involves operation of the VRAM, module controller, and LCD driver. Operation of an LSI device at a high frequency clock results in through-current flowing to the plural CMOS devices used as circuit elements, increasing the total current consumption. Total current consumption also increases in direct proportion to the size of the LCD panel. In addition, while the VRAM is accessed by both the MPU and the module controller, a high speed clock must be used so that MPU access during the display refresh operation does not collide with module controller access, thus limiting the use of a low frequency operating module controller and limiting the processing ability of the MPU.
Operation at a low frequency clock is possible in the latter method above because there is no relationship between display data transfer and LCD timing. This method thus requires 10-100 times less power than the module controller method. When using a large liquid crystal panel, however, the number of X drivers must be increased.
The number of X driver output terminals is generally a multiple of ten (e.g., 160 pins) and not a power of two (e.g., 2n), however, because each RAM device built in to the X drivers has an independent address area. When the internal memory of plural X drivers is addressed by the MPU, the MPU finds apparent gaps in the total memory area, and it is usually difficult to maintain a continuous sequence of addresses. As a result, the address coordination process of the MPU must be executed at high speed when the entire display area is changed at one time as during scrolling or panning operations, significantly increasing the processing load on the MPU.
It is, of course, possible to design the X driver ICs to have an exponent-of-two number of output pins, but this would seriously impair system interchangeability because compatibility with the number of electrodes in existing LCD panels would be lost. In addition, use of plural X drivers necessarily increases the number of chip selection buses, and sufficient space for this plural number of X drivers to be installed around the LCD panel must be provided. This reduces the display area ratio of the display panel, and inhibits the potential size reduction of the LCD module. The latter method above is therefore unsuited to large scale liquid crystal panels.
Therefore, an object of the present invention is to provide a matrix display apparatus, a matrix display control apparatus, and a matrix display drive apparatus suited to a low power consumption, large capacity display by improving the display data transfer method.
The present invention provides a method combining a module controller-type display device with a signal electrode (X) driver having a built-in frame memory that intermittently operates the oscillation source of a high frequency clock for the module controller during display data transfer.
Specifically, a matrix display apparatus according to the invention comprises a matrix display device of display elements arranged in a matrix pattern, a first random access memory device for storing the display data, a second random access memory device for storing the display data of at least part of the display elements, and a signal electrode drive means for reading the display data from the second memory device to apply a drive voltage to the signal electrodes of the matrix display device. This matrix display apparatus is characterized by an intermittent high frequency oscillator that oscillates according to changes in the display data stored in the first RAM device, and a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.
The matrix display control apparatus for this display apparatus comprises a low frequency oscillator for constantly generating a low frequency clock, a timing signal generator for generating a specified timing signal based on the low frequency clock from the low frequency oscillator, a display data refresh detection means for generating an intermittent control signal based on changes in the display data stored in the first RAM device, an intermittent high frequency oscillator that oscillates according to the intermittent control signal, and a display data transfer means for reading the display data associated with the change from the first RAM device according to the high frequency clock output from the intermittent high frequency oscillator, and transferring the read display data together with the high frequency clock to the second RAM device.
A matrix display drive apparatus comprising a second random access memory device for storing the display data of at least part of the display elements, reading the display data from the second RAM device, and applying a drive voltage to the signal electrodes of the matrix display device, and used in a display apparatus using this matrix display control apparatus comprises a timing signal generator for generating a write control signal and a read control signal at an offset timing within one scanning period based on the cycle signal received each scanning period, and a read/write means for executing a read operation according to the read control signal and then executing a write operation according to the write control signal with both operations addressing the same address in the second RAM device.
A matrix display drive apparatus of this type preferably comprises a clock detection means for detecting when the high frequency clock used for display data transfer stops, and a write prohibit control means for preventing generation of the write control signal based on this detection signal.
The read/write means of this matrix display drive apparatus comprises a temporary storage means for sequentially storing at least one scan line of the incoming display data using the high frequency clock, and a buffer for writing to the second RAM device the stored display data from the temporary storage means according to a signal longer than one cycle of the high frequency clock.
In a matrix display drive apparatus using a multiple line selection drive method, the read/write means comprises a signal voltage state assignment means for extracting the signal voltage to be applied to the signal electrode from the display data read from the second RAM device and the voltage state of the scanning electrode of the matrix display device.
This signal voltage state assignment means specifically comprises a means for reading plural scan lines of display data from the second RAM device on a time-share basis, a temporary storage means that alternately waits for the read display data, a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device, an anti-coincidence detector for detecting anti-coincidence between the plural scan line equivalent display data and the selected voltage state of the scan electrode, and a voltage selector for selecting the signal electrode voltage based on the anti-coincidence detection result.
In a differently configured matrix display drive apparatus using a multiple line selection drive method, the second RAM device comprises a memory array for storing plural scan lines of display data for one line address of the matrix display device, and the signal voltage state assignment means comprises a means for batch reading plural scan lines of display data, a scan state setting means for specifying the voltage state of the scan electrode of the matrix display device, and a voltage selector for selecting the drive voltage from the plural scan line display data read from the second RAM device and the selected voltage state of the scan electrode.
The present invention configured for a uniform distribution, multiple line selection drive method for a scan electrode drive apparatus using a multiple line selection drive method is characterized by a means for simultaneously selecting and cyclically scanning plural scan electrodes plural times within the period of the frame start signal.
A matrix display control apparatus thus comprised can reduce the total power consumption because of intermittent operation of the high frequency clock because the high frequency clock operates only when there is a change in the display data stored in the first RAM device, at which time the display data is transferred to the second RAM device. The processing load on the host MPU for the first RAM device can also be reduced because the transfer process to the second RAM device is executed not by the MPU but by an intermediary matrix display control apparatus. By cascade connecting the drive device of the signal electrodes, display data can be transferred according to the configuration of the matrix display device without being aware of the driver side memory configuration, and the address correlation process can be simplified. The display can also be refreshed faster because the display data for each scan line is stored in the second RAM device. By cascade connecting the signal electrode drive devices, the number of connections (e.g., the number of chip selection buses) between the matrix display control apparatus and drive devices can be minimized even in large capacity displays, and display devices with a large display area ratio can be achieved.
In addition, the second RAM device can be accessed with ease using time-share access timing during one scanning period. Greater tolerance is therefore achieved in the second RAM device access timing, improving data writing performance and making it possible to reduce the size of the transistors in the second RAM device. This also contributes to a reduction in driver chip size.
Other objects, advantages and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.